module REG_EX_MEM (
    input clk,
    input rst_n,
    
    input [2:0] wd_sel_i,
    input rf_we_i,
    input dram_we_i,
    input [4:0] wR_i,
    input [31:0] wD_i,
    input [31:0] aluc_i,
    input [31:0] rD2_i,
    input [3:0] load_sel_in,
    input [2:0] store_sel_in,
    input [1:0] offset_in,

    output reg [3:0] load_sel_out,
    output reg [2:0] store_sel_out,
    
    output reg [2:0] wd_sel_o,
    output reg rf_we_o,
    output reg dram_we_o,
    output reg [4:0] wR_o,
    output reg [31:0] wD_o,
    output reg [31:0] aluc_o,
    output reg [31:0] rD2_o,
    output reg [1:0]  offset_out,

    input      [31:0] pc_i,
    output reg [31:0] pc_o,
    input             debug_have_inst_i,
    output reg        debug_have_inst_o
    );

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      load_sel_out <=  3'b0;
        else            load_sel_out <= load_sel_in;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      store_sel_out <=  2'b0;
        else            store_sel_out <= store_sel_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)  pc_o <= 32'b0;
        else        pc_o <= pc_i;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)  debug_have_inst_o <= 1'b0;
        else        debug_have_inst_o <= debug_have_inst_i;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      wd_sel_o <= 2'b0;
        else            wd_sel_o <= wd_sel_i;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      offset_out <= 2'b0;
        else            offset_out <= offset_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      rf_we_o <= 1'b0;
        else            rf_we_o <= rf_we_i;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      dram_we_o <= 1'b0;
        else            dram_we_o <= dram_we_i;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      wR_o <= 5'b0;
        else            wR_o <= wR_i;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      wD_o <= 32'b0;
        else            wD_o <= wD_i;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      aluc_o <= 32'b0;
        else            aluc_o <= aluc_i;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      rD2_o <= 32'b0;
        else            rD2_o <= rD2_i;
    end

endmodule
